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Thus, the CPU 22 executes the program as a CPU process.
Note that the above microcomputer operates in the same manner as a general-purpose computer, when it is provided with an instruction prefetch mechanism, an instruction cache memory, a general-purpose register, a data cache memory, a data prefetch mechanism, a memory access mechanism, etc.
The first and second operating modes are actually realized by setting a correspondence between the instructions stored in the instruction storage unit 26 of the CPU 22 and the instruction area of the program storage unit 25.
An instruction given to the microcomputer by the user is prefetched by the instruction prefetch mechanism, and stored in the instruction cache memory 32.
The CPU 22 then reads out a desired instruction from the instruction cache memory 32, and executes the instruction.
By virtue of this, the instruction can be executed at a high speed.
FIG. 3 is a block diagram illustrating the first embodiment of the invention. In the figure, the same reference numerals denote the same components as those in FIG. 1.
In FIG. 3, the CPU 22 is arranged to have the first operating mode, the address bus ADR being connected to the external memory device 17 and the instruction prefetch mechanism 30.
The CPU 22 is also provided with the second operating mode, the address bus ADR being connected to the instruction prefetch mechanism 30 and the program storage unit 25.
In the microcomputer of FIG. 3, when the first operating mode is set, the external memory device 17 and the instruction prefetch mechanism 30 are driven by the address bus ADR.
When the second operating 0b46394aab
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